Curriculum Vitae
I’m a fifth-year Ph.D. student at MIT. My current research area is in the modeling and design of specialized accelerators for machine learning. My work has included novel compute paradigms, including analog, compute-in-memory, optical, and superconducting accelerators. Currently I’m working on tools to optimally schedule deep neural network workloads onto specialized accelerators and applying these tools to novel and heterogeneous systems.
Education
- 2021–2027 (est.) Ph.D. Electrical Engineering & Computer Science, Massachusetts Institute of Technology
- Advised by Profs. Joel Emer and Vivienne Sze
- 2023 Certificate in Innovation Leadership, Santa Clara University
- 2023 Forklift Certified
- 2021–2023 M.S. Electrical Engineering & Computer Science, Massachusetts Institute of Technology
- 5.0/5.0 GPA
- Master’s thesis: Efficient, Accurate, and Flexible PIM Inference through Adaptable Low-Resolution Arithmetic
- 2017–2021 B.S. Computer Engineering, Purdue University West Lafayette
- 3.97/4.0 GPA, Graduated Summa Cum Laude
- 2017–2021 B.S. Mathematics, Purdue University
- 3.97/4.0 GPA, Graduated Summa Cum Laude
Research Experience
- 2024–Present Optimal mapping of deep neural network workloads on hardware
- Developing algorithms that can find optimal ways to map deep neural network workloads onto hardware, a problem previously thought intractable.
- Exploring novel mapspaces.
- 2024–Present Architecture design for superconducting accelerators
- 2021–Present Analog/digital compute-in-memory accelerator design & modeling
- Developing full-stack simulation tools for compute-in-memory accelerators of tensor algebra and deep neural network workloads.
- Released open-source tools modeling analog devices and compute-in-memory arrays.
- Enabling co-design and fast design space exploration for these architectures.
- 2019–2021 On-chip interconnect interference modeling
- Advised by Prof. Cheng Kok Koh, Purdue University.
- Developed computationally efficient models of inductive/capacitive interference in on-chip interconnects.
- Lowered the computational complexity bound from O(N²) to O(N) for accurate simulation of N-wire systems.
- 2018–2019 Purdue VIP Smart Cities autonomous drone research
- Advised by Prof. Mohammad Reza Jahanshahi, Purdue University.
- Developed simulators to test autonomous drone piloting algorithms.
- Using this infrastructure, explored reinforcement learning algorithms to operate building-scanning drones.
Work Experience
- May–August 2024 Ph.D. Research Intern, Nvidia Circuits Research Group
- Developed tools that automatically optimize how deep neural networks are programmed onto accelerators.
- Developed a method to find optimal DRAM-access-minimizing programs.
- May–August 2020 Digital Hardware Intern, Qualcomm Technologies, Incorporated
- Worked with the digital design infrastructure team to develop processor-memory interface systems.
- Developed tools to automate digital design processes for processor-memory interface systems.
- May–August 2019 Software and Controls Intern, Eaton Corporation
- Developed diagnostic software and automating scripts to improve testing process of semi-truck control software.
- Authored tools for retrieval of memory contents and diagnosis of errors in semi-truck computer memory.
Teaching
- 2024–2025 Graduate Teaching Assistant, MIT 6.5930 Hardware Architectures for Deep Learning
- Jan–May 2021 Undergraduate Teaching Assistant, Purdue ECE 50863-EDX Computer Network Systems
- Led the design of new student programming projects based on cutting-edge computer network research.
- Tested and modified student assignments for online instruction.
- Designed systems to support Internet Systems Lab research. Implemented lightweight methods to enable transmission and sharing of flows over multiple tunnels in software-defined networks.
Service
- Program committee member: HPCA 2026, MICRO 2026
- Reviewer: TCASAI 2026, CAL 2026, CAL 2025
Selected Awards
- 2024 ISPASS Best Paper Award: CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool
- 2023 Samsung Semiconductor Fellowship
- 2022 MIT Siebels Scholar Fellowship
- 2021 MIT Irwin Mark Jacobs and Joan Klein Jacobs Presidential Fellow
- 2021 Purdue Undergraduate Excellence Award, awarded for contributions in creating the ECE-50863 EDX course
- 2017–2021 Purdue Fessenden Trott Scholarship
- 2017–2021 Purdue Presidential Scholarship
Activities
- 2021–2023 MIT Rock Climbing Team
- 2021–Present MIT GSB Organizer
- Social event organizer for the MIT Computer Science & Artificial Intelligence Laboratory (CSAIL).
- 2021–2023 MIT Edgerton House Board Member and Resources Chair
- 2019–2021 Purdue IEEE Remote Operated Vehicle Team
- Designed control algorithms for autonomous submarine thruster systems. Enabled submarine to do a backflip for the first time in competition.
- Developed computer vision algorithms that enabled autonomous submarine to recognize and react to underwater objects.
- 2018–2019 Purdue IEEE Aerial Robotics Team
- Lead designer of collision-avoidance algorithms to pilot autonomous planes between skyscrapers.
Publications and Talks
- LoopForest: Exploring an Expanded Fusion Mapspace for Reduced Data Movement and Memory Usage
- Small-Noise is All You Need: Fast and Precise Estimation of Compute-in-Memory Accuracy Loss
- Fast and Fusiest: An Optimal Fusion-Aware Mapper for Accelerator Design
- The Turbo-Charged Mapper: Fast and Optimal Mapping for Energy-efficient and Low-latency Accelerator Design
- CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool
- Architecture-Level Modeling of Photonic Deep Neural Network Accelerators
- Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design
- Efficient, Accurate, and Flexible PIM Inference through Adaptable Low-Resolution Arithmetic!
- Efficient AI Inference With Analog Processing In Memory
- RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required!
- Architectural Evaluation of Processing-In-Memory Systems